SiliconBrite is seeking an experienced layout engineer that will perform analog & mixed-signal (AMS) IC layout according to engineering specifications and by using the Cadence Virtuoso EDA tool.
- Design of chip layout and complete set of design verification for various analog mixed-signal circuits (individual blocks to full-chip level).
- Manage in-house developed IP library and optimization of layout implementation techniques.
- Solid knowledge of Physical verifications, debug, and parasitic extractions including LVS/DRC.
- Analyze and review floor planning/schematics with responsible IC designers.
- Bachelor of Science in Electrical Engineering or equivalent.
- At least 15 years of direct experience working with semiconductor companies.
- Good understanding of the Cadence EDA toolset.
- Basic knowledge of AMS circuits is preferred.
- Strong analytical and communication skills.
- Self-starter and excellent team player.
- The position can be based in San Jose, CA, or a remote location globally.
If you’d like to be considered for this position, please send your resume to info@siliconbrite.com or click the apply button below.